1. Field of the Invention
The present invention relates to multiport memory cells. More particularly, the present invention relates to a multiport memory cell using a small differential voltage for write operation and a single addressable port for both read and write operation, and having read current amplification to precharge bit lines and to allow for simultaneous reads in case of address coincidence.
2. The Prior Art
Multiport CMOS memory cells are known in the art. Such memory cells permit sharing of memory by providing for a large number of ports for read and write operations. For example, one such multiport memory cell is discussed in the IEEE Journal of Solid-State Circuits, vol. 26, no. 10, October 1991. Such a multiport memory cell is shown in FIG. 1. It is a nine-ported memory cell and has associated read and write circuitry.
The nine-ported memory cell of this prior art memory cell uses common bit and word lines for read and write operations, so they are performed in succession. The memory cell can be connected to six bit lines through N-channel MOS pass transistors. This configuration provides six read ports (one bit line per port) and three write ports (two bit lines per port).
Despite the existence of the above multiport memory cell, there remains room for improvement in minimizing the voltage required for a write operation while ensuring cell stability and reliability of the multiport memory cell during a read operation.
Thus, it is an object of this invention to provide a multiport memory cell using a small differential voltage during write operations while ensuring nondestructive reads of the memory cell.
It is another object of this invention to provide a multiport memory cell using a single addressable pod for both read and write operation per storage node.
It is another object of this invention to provide a multiport memory cell that provides for precharging bit lines and for simultaneous read operations.